The present invention relates to a plasma display and method of driving the same.
A plasma display (to be referred to as a PDP hereinafter) performs display on the basis of discharge emission, and hence can have a low-profile structure. In addition, the PDP can have a high display contrast and relatively large screen without any flicker. The PDP is of a spontaneous emission type having a high response speed and can perform multicolor emission by using phosphors. Owing to these characteristics, the PDP has recently been used in many fields, e.g., the field of display apparatuses associated with computers and the field of color image display.
Such PDPs are roughly classified, according to operation schemes, into AC discharge type PDPs in which electrodes are coated with dielectric layers and indirectly operated in an AC discharge state and DC discharge type PDPs in which electrodes are exposed in a discharge space and operated in a DC discharge state.
The AC discharge type PDPs are classified, according to driving schemes, into memory-driven PDPs designed to cause discharge by using the display information stored in memories mounted on panels themselves and refresh PDPs designed to repeatedly read out display information from external memories and output the information to panels so as to perform discharge display. The memory-driven PDPs suited for large-capacity display have currently become mainstream.
The brightness of the PDP is proportional to the number of times of discharge on the panel. In the refresh PDP, therefore, as the display capacity increases, the number of times of discharge decreases, resulting in a reduction in brightness. For this reason, the refresh operation scheme is used for PDPs with small display capacities.
FIG. 13 shows one display cell of a general AC discharge memory-driven PDP.
Referring to FIG. 13, a display cell 1 has insulating substrates 11 and 12 which are front and rear surfaces made of glass. Components such as electrodes are formed between the insulating substrates 11 and 12. More specifically, a scan electrode 13 and sustain electrode 14 which are made of transparent conductive films are selectively formed under the insulating substrate 11, and trace electrodes 15 and 16 made of metal conductive films are formed under the scan electrode 13 and sustain electrode 14 to reduce the resistances of the scan electrode 13 and sustain electrode 14. The scan electrode 13, sustain electrode 14, and trace electrodes 15 and 16 are covered with a transparent dielectric layer 20. A protective layer 21 made of a magnesium oxide is formed on the entire lower surface of the dielectric layer 20 to protect the dielectric layer 20 against discharge caused by a discharge gas.
A discharge gas space 18 filled with a discharge gas such as helium, neon, xenon, or a gas mixture thereof is formed under the protective layer 21. A phosphor 19 for converting ultraviolet rays produced by discharge caused by the discharge gas into visible light 23 is formed under the discharge gas space 18. A dielectric layer 22 is formed under the phosphor 19. A data electrode 17 is formed between the dielectric layer 22 and the insulating substrate 12.
Note that the scan electrode 13 in FIG. 13 corresponds to each of reference symbols Sc and Sc1 to Scm in each drawing to be described later. The sustain electrode 14 in FIG. 13 corresponds to each of reference symbols Su and Su1 to Sum in each drawing to be described later. The data electrode 17 in FIG. 13 corresponds to each of reference symbols Di and D1 to Dn in each drawing to be described later.
FIG. 14 shows the schematic arrangement of an AC discharge memory-driven PDP.
Referring to FIG. 14, the PDP is comprised of a panel 2 made up of display cells 1, each shown in FIG. 13, arranged in the form of a matrix, control circuit 3 for controlling the display operation of the panel 2, scan driver 4 for driving the scan electrodes Sc1 to Scm of the respective display cells 1, sustain driver 5 for driving the sustain electrodes Su1 to Sum of the respective display cells 1, and address driver 6 for driving the data electrodes D1 to Dn of the respective display cells 1.
The control circuit 3 is constituted by a frame memory 31 for storing display data, signal processing circuit 32 for performing signal processing and outputting the resultant data to the address driver 6, and driver control circuit 33 for controlling the scan driver 4 and sustain driver 5.
The panel 2 is a dot matrix display panel having the display cells 1 arranged on m rows and n columns. This panel has row electrodes constituted by the scan electrodes Sc1 to Scm and sustain electrodes Su1 to Sum which are parallel to each other, and column electrodes constituted by the data electrodes D1 to Dn crossing the electrodes Sc1 to Scm and Su1 to Sum at right angles. The display cells 1 are formed at the intersections of the row and column electrodes.
The scan electrode driving waveforms generated by the scan driver 4 are applied to the scan electrodes Sc1 to Scm. The sustain electrode driving waveforms generated by the sustain driver 5 are applied to the sustain electrodes Su1 to Sum. The data electrode driving waveforms generated by the address driver 6 are applied to the data electrodes D1 to Dn.
The signal processing circuit 32 of the control circuit 3 generates control signals for the scan driver 4 and sustain driver 5 on the basis of external fundamental signals (a vertical sync signal Vsync, horizontal sync signal Hsync, clock signal Clock, and data sync signal DATA). These control signals are supplied to the respective drivers 4 and 5 through the driver control circuit 33. The data to be displayed on the display cell 1 is extracted from the frame memory 31 by the signal processing circuit 32 in synchronism with the clock signal Clock and data sync signal DATA, and is supplied to the display cell 1 through the address driver 6.
The write discharge operation of the display cell 1 having the above arrangement will be described next.
So-called write discharge is caused in the display cell 1 in which a pulse voltage exceeding a discharge threshold is applied between the scan electrode 13 and the data electrode 17. At this time, since both the electrodes 13 and 17 are covered with the insulating layers, positive and negative charges are stored on the surfaces of the dielectric layers 20 and 22 on the two sides to generate wall charges. These wall charges decrease the effective voltage in the cell. As a consequence, the discharge in the cell is terminated within a short period of time.
In sustain discharge operation dominating emission display, a sustain pulse having the same polarity as that of the voltage based on the wall charges is applied between the adjacent scan electrode 13 and sustain electrode 14. With this operation, since the sustain pulse voltage is superimposed on the voltage based on the wall charges, even if the sustain pulse voltage is low, the resultant voltage exceeds the discharge threshold between the scan electrode 13 and the sustain electrode 14. As a consequence, discharge occurs. If, therefore, sustain pulses are kept alternately applied to the scan electrode 13 and sustain electrode 14, the discharge between the electrodes can be maintained.
Sustain discharge can be quickly stopped by applying a low-voltage pulse having a large pulse width which cancels out the voltage based on wall charges or erase pulse having a small pulse width and a voltage near the sustain pulse voltage to the scan electrode 13 or sustain electrode 14.
FIGS. 15A to 15F show the first conventional example of the driving operation of the AC discharge memory-driven PDP in FIG. 14. In the first conventional example, write discharge and sustain discharge are caused at different timings.
FIGS. 15A shows a sustain pulse Wc applied to the sustain electrodes Su1, Su2, . . . , Sum. FIGS. 15B to 15E show scan pulses Ws1 to Wsm (only the pulses Sw1 to Ws4 are shown) respectively applied to the scan electrodes Sc1, Sc2, . . . , Scm. FIG. 15F shows a data pulse Wd applied to a data electrode Di (1xe2x89xa6ixe2x89xa6n).
One period (one subframe) of the driving operation of the panel 2 is constituted by four timings of priming discharge, write discharge, sustain discharge, and sustain discharge erase operation. Desired video display can be performed by repeating driving operation at each timing.
First of all, to obtain stable write discharge characteristics, priming discharge is caused to generate activated particles and wall charges in the discharge gas space. In this priming discharge, priming pulses Pp (FIG. 15A) are applied to make all the display cells of the panel 2 cause discharge at once, and priming erase pulses Ppe are simultaneously applied to the respective scan electrodes to eliminate charges, of the generated wall charges, which interfere with write discharge and sustain discharge (FIGS. 15B to 15E).
More specifically, the priming pulses Pp are applied to the sustain electrodes Su1, Su2, . . . , Sum of the respective display cells to make all the display cells cause discharge. Thereafter, the priming erase pulses Ppe are applied to the scan electrodes Sc1, Sc2, . . . , Scm to cause erase discharge to eliminate the wall charges stored upon application of the priming pulses Pp.
Subsequently, write discharge is performed. In write discharge, scan pulses Pw are sequentially applied to the scan electrodes Sc1, Sc2, . . . , Scm of the respective display cells 1 (FIGS. 15B to 15E). Data pulses Pd are selectively applied to the data electrodes Di (1xe2x89xa6ixe2x89xa6n) of the cells to perform display in synchronism with the scan pulses Pw (FIG. 15F).
After the above write discharge, negative sustain pulses Pc are sequentially applied to a sustain electrode, scan electrode, sustain electrode, . . . in the order named so as to cause sustain discharge required to obtain desired brightness. To stop sustain discharge, erase pulses Pse (pulse width of about 0.5 xcexcs to 1 xcexcs) are applied to stop the erase pulses before sufficient wall charges for sustain discharge are formed. With this operation, subsequent sustain discharge is stopped.
FIGS. 16A to 16G show the second conventional example of the driving operation disclosed in Japanese Patent Laid-Open No. 7-162787. Similar to the first conventional example, the second conventional example is associated with an AC discharge memory-driven PDP. In this case, write discharge and sustain discharge are simultaneously controlled by different scan electrodes.
FIG. 16A shows a data pulse An applied to a data electrode Di (1xe2x89xa6ixe2x89xa6n) of each display cell. FIGS. 16B, 16D, and 16F show sustain pulses C1, C2, C3, . . . , Cm (only the pulses C1 to C3 are shown) applied to sustain electrodes Su1, Su2, . . . , Sum of the respective display cells. FIGS. 16C, 16E, and 16G show scan pulses S1, S2, S3, . . . , Sm (only the pulses S1 to S3 are shown) respectively applied to the scan electrodes Sc1, Sc2, . . . , Scm.
In write discharge, scan pulses Pw are sequentially applied to the scan electrodes Sc1, Sc2, . . . , Scm of the respective display cells 1 (FIGS. 16C, 16E, and 16G). In synchronism with these scan pulses Pw, data pulses Pd are selectively applied to the data electrodes Di (1xe2x89xa6ixe2x89xa6n) of the cells selected for display (FIG. 16A). With this operation, write discharge is caused in the cells selected for display to generate wall charges. Sustain pulses Ps are sequentially applied to the respective scan electrodes having undergone write discharge in the order of a sustain electrode, scan electrode, sustain electrode, . . . , thereby maintaining sustain discharge.
In the second conventional example, since pixel data pulses can be applied while sustain pulses are applied to electrodes other than electrodes for a write, the write cycle of pixel data can be shortened without shortening the pulse width of each scan pulse and the pulse width of each sustain pulse.
In the second conventional example, the voltage used to cause write discharge is the sum of a scan pulse voltage VS and data pulse voltage VD, and hence must be higher than the discharge start voltage between a scan electrode Y and data (column) electrode D and high enough to generate sufficient wall charges for a shift to sustain discharge.
In general, data pulses are repeatedly turned on and off with respect to all scanning lines, whereas scan pulses are generated one by one for each scan line every time display image is updated. For this reason, the power consumption associated with data pules is much higher than that associated with scan pulses. For this reason, a method of increasing the scan pulse voltage as high as possible and decreasing the data pulse voltage is used. In order to increase the scan pulse voltage, however, a driving circuit with a high breakdown voltage is required. Such a driving circuit is expensive, and hence the cost of a display apparatus increases.
FIGS. 17A to 17G show the third conventional example of the driving operation disclosed in Japanese Patent Laid-Open No. 6-337654. The third conventional example is associated with an AC discharge memory-driven PDP, in which wall charges are generated by applying wall charge generation pulses to sustain electrodes immediately after write discharge.
FIGS. 17B, 17D, and 17F show sustain pulses C1, C2, C3, . . . , Cm (only the pulses C1 to C3 are shown) commonly applied to sustain electrodes Su1, Su2, . . . , Sum of display cells 1. FIGS. 17C, 17E, and 17G show scan pulses S1, S2, S3, . . . , Sm (only the pulses S1 to S3 are shown) respectively applied to scan electrodes Sc1, Sc2, . . . , Scm of the respective display cells 1. FIGS. 17A shows a data pulse An applied to a data electrode Di (1xe2x89xa6ixe2x89xa6n) of each display cell 1.
In write discharge, scan pulses Pw are sequentially applied to the respective scan electrodes Sc1, Sc2, . . . , Scm (FIGS. 17C, 17E, and 17G). In synchronism with these scan pulses Pw, data pulses Pd are selectively applied to data electrodes Di (1xe2x89xa6ixe2x89xa6n) of the display cells selected for display (FIG. 17A). Wall charge generation pulses Pk, each having a polarity opposite to that of the scan pulse Pw, are applied to the sustain electrodes Su1, Su2, . . . , Sum immediately after the application of the scan pulses Pw (FIGS. 17B, 17D, and 17F), thereby generating wall charges.
In the third conventional example, in write discharge operation, a pulse for causing discharge between a data (column) electrode and a scan (Y) electrode is separated from a pulse for generating wall charges between the scan (Y) electrode and a sustain (X) electrode. For this reason, the write cycle of image data can be shortened by decreasing the pulse width of each scan pulse.
In the third conventional example, as in the second conventional example, since the voltage for causing write discharge is the sum of a scan pulse voltage VS and data pulse voltage VD, this voltage must be set to be higher than the discharge start voltage between the scan electrode Y and the data (column) electrode D.
To solve this problem, a method of increasing the scan pulse voltage as high as possible and decreasing the data pulse voltage is used. In order to increase the scan pulse voltage, however, a driving circuit with a high breakdown voltage is required. Such a driving circuit is expensive, and hence the cost of a display apparatus increases.
As described above, in the first conventional example in which write discharge and sustain discharge are caused at different timings, although scan pulses and data pulses are simultaneously applied, sustain pulses and data pulses are not simultaneously applied. For this reason, write discharge and sustain discharge can be caused independently, and hence can be stably controlled. However, since sustain discharge periods cannot be used as write discharge periods, the use of write discharge periods is limited. This makes it difficult to realize a high-resolution panel and multilevel gray-scale display while properly coping with high frame frequencies.
In the second and third conventional examples in which write discharge and sustain discharge are simultaneously controlled by using different scan electrodes, since sustain discharge periods can also be used as write discharge periods, the write discharge periods can be prolonged. However, since a driving circuit with a high breakdown voltage is required for write discharge, the cost of the system increases.
It is an object of the present invention to provide a plasma display which improves write discharge and sustain discharge characteristics and driving method for the display.
It is another object of the present invention to provide a plasma display which can be realized by an inexpensive driving circuit, and driving method for the display.
In order to achieve the above objects, according to the present invention, there is provided a plasma display comprising a matrix electrode section including a plurality of scan electrodes, a plurality of sustain electrodes arranged parallel to the scan electrodes, and a plurality of data electrodes crossing the scan and sustain electrodes at right angles, a plurality of display cells formed at the intersections of the scan electrodes, the sustain electrodes, and the data electrodes, and a plurality of driving means connected to the scan electrodes, the sustain electrodes, the data electrodes to drive the display cells, each of the driving means including first and second switching means for alternately applying first and second sustain pulses respectively having positive and negative potentials with respect to a reference potential of the data electrode to the scan and sustain electrodes such that a potential relationship between the scan and sustain electrodes is periodically reversed, third switching means for applying a scan pulse having a negative potential higher than the potential of the second sustain pulse to the scan electrode to superimpose the scan pulse on the second sustain pulse, fourth switching means for applying a semi-selection pulse having a potential lower than the potential of the first sustain pulse to the sustain electrode corresponding to the scan electrode when a scan pulse is applied to the scan electrode, and fifth switching means for selectively applying a data pulse having a positive potential with respect to the reference potential of the data electrode to the data electrode in accordance with a timing at which a scan pulse is applied to the scan electrode.